2016 International Conference on Analog VLSI Circuits

Advance Program

August 24, 2016

08:15-	Security Desk Check-in (1F) / Registration (5F)
09:00-09:15	Opening ceremony
09:15-10:15	Keynote 1: Interconnect technologies for high bandwidth ICT systems Dr. Norio Chujo (Hitachi, Ltd.) Chairperson: Toshihiko Hamasaki (Hiroshima Institute of Technology)
10:35-11:50	Technical Session: Converters 1 1-1 Experimental Implementation of β-Expansion Cyclic ADC with Correlated Level Shifting Technique Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe (Tokyo City University), Tatsuji Matsuura(Tokyo University of Science), Hao San, Masao Hotta(Tokyo City University) 1-2 A 14-bit 80ksps Cyclic ADC Based on β-expansion Yuki Watanabe, Hayato Narita, Junpei Uchita, Hiroyuki Tsuchiya (Tokyo City University), Tatsuji Matsuura (Tokyo University of Science), Hao San, Masao Hotta (Tokyo City University) 1-3 Non-Binary and Binary Weighted Hybrid Pipeline ADC with β estimation Takuma Suzuki (Tokyo University of Science), Hao San (Tokyo City University), Akira Hyogo, Tatsuji Matsuura (Tokyo City University) Chairperson: Akira Yasuda (Hosei University)
11:50-13:30	Lunch
13:30-15:10	Technical Session: Converters 2 2-1 Three-Step Incremental delta sigma A/D converterIncluding Sample-and-Hold circuit Hiroshi Endo, Tatsuji Matsuura, Akira Hyogo (Tokyo University of Science) 2-2 Ultra-Low-Voltage High-Speed ADCs James Lin (Analog Devices, Inc.), Masaya Miyahara, Akira Matsuzawa (Tokyo Institute of Technology) 2-3 Analysis and Design of High-SNDR VCO-based ADC in advanced CMOS Yu Hou, Masaya Miyahara, Akira Matsuzawa (Tokyo Institute of Technology) Akira Shikata (Analog Devices, Inc.) 2-4 Implementation and Measurement of a Delta-Sigma DAC with a Jitter Shaper Reducing Jitter Noise Ryosuke Minemura, Satoshi Saikatsu, Go Harumi, Michitaka Yoshino, Akira Yasuda (Hosei University) Chairperson: Hao San (Tokyo City University)
15:30-16:45	Technical Session: Analog Circuits 1 3-1 Design of Reference Voltage Generator for SFADC with Dynamic Element Matching Toshiki Sugimoto, Hiroshi Tanimoto, Shingo Yoshizawa (Kitami Institute of Technology) 3-2 Third-Order Mismatch Shaping Technique with Improved Small Amplitude Input Performance for a Digitally Driven Speaker System Yuki Hatsude, Go Harumi, Satoshi Saikatsu, Michitaka Yoshino, Akira Yasuda (Hosei University) 3-3 Accurate Nanopower Supply-Insensitive CMOS Unit Vth and αVth Extractors Jing WANG, Hirofumi SHINOHARA, Yasuaki INOUE (WASEDA University) Chairperson: Takeshi Shima (Kanagawa University)

August 25, 2016

08:30-	Security Desk Check-in (1F) / Registration (5F)
09:00-10:00	Keynote 2: Perverse Trends in Analog Technology, Dr. Chris MANGELSDORF (Analog Devices, Inc.) Chairperson: TBA
10:00-10:30	Invited talk: Open Source LSI Design & Fabrication Project for Distributed IP Development Junichi Akita (Kanazawa University) Chairperson: TBA
10:50-12:05	Technical Session: CAD and Image Sensor 4-1 Cloud-based Analog LSI CAD system for cooperative design Seijiro Moriyama, Manabu Ishibe (Anagix Corporation), Chikau Takahashi (Takamori Co., Ltd.), Michitaka Yoshino, Akira Yasuda (Hosei University) 4-2 Image Sensor Architecture and Component Circuits for High Speed Line-of-Sight Calculation Satoshi Yamamura, Junichi Akita (Kanazawa University) 4-3 3-D Depth Detection Camera System Using Time-of-Flight (TOF) Tomohisa Funabashi, Bin Huo, Erik Barnes (Analog Devices, Inc.) Chairperson: Hiroki Sato (Tokyo Institute of Technology)
12:00-13:30	Lunch
13:30-14:45	Technical Session: Analog Circuits 2 5-1 Low-Voltage and Linear CMOS Chopping Modulation Circuit for Chopper Stabilization Technique Hiroki SATO, Shigetaka TAKAGI (Tokyo Institute of Technology) 5-2 EMI reduction in DC-DC Converter using Hysteretic Control with Pseudo Analog Signal Koyo Asaishi, Nobukazu Takai (Gunma University), Yasunori Kobori (National Institute of Technology), Nobukazu Tsukiji, Naoya Shiraishi, Haruo Kobayashi (Gunma University) 5-3 VLSI Implementation of a Hardware CPG Model for Biped Robots Katsutoshi Saeki, Daisuke Nihei (Nihon University) Chairperson: Nicodimus Retdian (Shibaura Institute of Technology)
18:00	Boarding time of dinner cruise
19:00	Dinner cruise and award ceremony

August 26, 2016

08:30-	Security Desk Check-in (1F) / Registration (5F)
09:00-10:00	Keynote 3: Millimeter-wave CMOS Transceiver for 60-GHz Wi-Fi, 5G Cellular and future, Dr. Kenichi Okada (Tokyo Institute of Technology) Chairperson: Toshihiko Hamasaki (Hiroshima Institute of Technology)
10:20-12:00	Technical Session: RF and Logic Circuits 6-1 A 24-GHz Low-Noise Amplifier using Three-Ports Inductor Yoshiki Sato, Kiyotaka Komoku, Takayuki Morishita, Nobuyuki Itoh (Okayama Prefectural University) 6-2 A 25.8% Locking Range 24-GHz Injection Locked Frequency Divider with Switched Capacitors in 180-nm CMOS Yoshitake Nishino, Kiyotaka Komoku, Takayuki Morishita, Nobuyuki Itoh (Okayama Prefectural University) 6-3 A 2.4/5.25 GHz Concurrent Dual-Band LNA Equipped Matching Networks Using Mutual Induction Taishi Kitano, Takayuki Morishita, Kiyotake Komoku, Nobuyuki Itoh (Okayama Prefectural University) 6-4 Low Power Adiabatic Cascade Logic using FinFET Shu-hei Ohno, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Universit) Chairperson: Hiroshi Tanimoto (Kitami Institute of Technology)
12:00-13:30	Lunch
13:30-14:45	Technical Session: Amplifires 7-1 A Variable Overdrive Voltage CMOS Current Mirror for Low-Voltage Applications Akio Shimizu, Yohei Ishikawa (National Institute of Technology, Ariake College), Sumio Fukai (Saga University) 7-2 A Very Low-Power, Low-Noise, High-Speed Bipolar Amplifier for Precision ADC Drive Applications Kerry Phillips, Yukihisa Handa (Analog Devices, Inc.) 7-3 Time-Mode Miller Compensation Circuit using an Operational Transconductance Amplifier Nicodimus Retdian (Shibaura Institute of Technology), Kousuke Ooi, Takeshi Shima (Kanagawa University) Chairperson: Katsutoshi Saeki (Nihon University)
14:45-15:00	Closing ceremony

• Keynote: 60 mins for presentation and Q & A
• Invited talk: 25 mins for presentation, 5mins for discussion
• Regular presentation: 20 mins for presentation, 5mins for discussion